Author

Chaodan Deng

Date

October 1995

Document Type

Dissertation

Degree Name

Ph.D.

Department

Dept. of Electrical Engineering

Institution

Oregon Graduate Institute of Science & Technology

Abstract

Nanometer-scale devices have attracted great attention as the ultimate evolution of silicon integrated circuit technology. However, fabrication of nanometer-scale silicon based devices has met great difficulty because it places severe constraints on process technology. This is especially true for SiGe/Si heterostructures because they are particularly sensitive to strain relaxation and/or process induced defects. Recently developed Pulsed Laser Induced Epitaxy (PLIE) offers a promising approach for the fabrication of nanometer- scale SiGe/Si devices. It possesses the advantage of ultra-short time, low thermal budget and full compatibility with current silicon technology. The selective nature of the process allows epitaxial growth of high quality, localized SiGe layers in silicon. In this thesis, a process to fabricate SiGe nanowires in silicon using PLIE is described. In particular, Ge nanowires with a cross-section of ~6 x 60 nm² are first formed using a lift-off process on the silicon substrate with e-beam lithography, followed by a thin low-temperature oxide deposition. Defect-free SiGe nanowires with a cross-section of ~25 x 95 nm² are then produced by impinging the laser beam on the sample. We thus demonstrate PLIE is a suitable fabrication technique for SiGe/Si nanostructures. Fabrication of Ge nanowires is also studied using Focused Ion Beam (FIB) micromachining techniques. Based on the SiGe nanowire process, we propose two advanced device structures, a quantum wire MOSFET and a lateral SiGe Heterojunction Bipolar Transistor (HBT). MEDICI simulation of the lateral SiGe HBT demonstrates high performance of the device. In order to characterize the SiGe nanowires using cross-sectional transmission electron microscopy, an advanced versatile focused ion beam assisted sample preparation technique using a multi-layer stack scheme for localized surface structures is developed and described in this thesis.

Identifier

doi:10.6083/M4XS5S9K

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