Date

May 2005

Document Type

Thesis

Degree Name

M.S.

Department

Dept. of Computer Science and Electrical Engineering

Institution

Oregon Health & Science University

Abstract

With modem CMOS technology likely to reach physical limits in the next decade or so, researchers have been working on alternate approaches to continue semiconductor scaling. This next level would be at the nanoscale, that is, electronic devices with dimensions of a few nanometers, 10[superscript -9] of a meter. This thesis represents an early step in understanding one proposed implementation strategy for projected nanoscale devices. Although various architectures have been proposed, the most promising and interesting is that of a crossbar array with programmable cross points. A number of nanoscale crossbar devices ("nanoarrays") have been demonstrated. The use of such architecture is being researched at many levels and has yielded interesting results. Our work aims at studying the electrical properties, efficiency and reliability of the crossbar arrays for a particular type of memory structure. In the first phase of the research we began by simulating the physical and electrical properties of the silicon nanowire and testing a simple 2x2 crossbar array made of silicon nanowires. Based on fabrication constraints obtained from real arrays, we have estimated a maximum array size that can be achieved. In the second phase of the research we calculated the "RC" delays for the crossbar array network. In this phase we studied two different crossbar models - the "Molecular" model and the "Leiber" model, for estimating the delays. In the final phase of this work we have done preliminary defects analysis of both the models and estimated the tolerance level of the models for various defect densities.

Identifier

doi:10.6083/M41J97NG

School

OGI School of Science and Engineering

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