Date

April 1999

Document Type

Dissertation

Degree Name

Ph.D.

Department

Dept. of Computer Science and Engineering

Institution

Oregon Graduate Institute of Science & Technology

Abstract

In this dissertation, I study the use of context in sensory processing, and specifically, cost-effective parallel implementations of contextual processing. Taking contextual information to be represented in the form of discrete, compact models, application of contextual knowledge then occurs as models are matched to input. Model-matching occurs at the interface between bottom-up classification and feature extraction and top-down modeling and interpretation. Bottom-up classification and feature extraction can be well supported by cost-effective parallel hardware. The central thrust of this dissertation is to show how such parallel hardware can be inexpensively modified to support model-matching, thus extending its range of applicability. For contextual processing of ordered input, I derive "Higher Order Viterbi Search (HOVS)", a Markov approximation to Viterbi search using higher-order source models. Simulations show HOVS captures most of the benefit of using higher order source models, while being more time and space efficient. I give an SIMD implementation of HOVS, and discuss some restrictions on the source model required for a practical implementation. From analysis of algorithm requirements and VLSI trends, with area as cost measure, I derive a cost-performance model for on-chip parallelism. I conclude that for the applications considered, there are only two viable architectural alternatives: if the required system memory fits on-chip, using many simple processors may be preferred. Otherwise, off-chip bandwidth limitations imply an architecture of a few complex processors. I introduce the SFMD class of parallel architectures, extending SIMD processing to better handle the irregular, data-dependent computation typical of contextual processing. SFMD extends SIMD processing by giving each processing element separate control within small loop bodies. The extra processor complexity is modest. To preserve SIMD semantics and programming simplicity, interprocessor communications may complete only after all processors have synchronized at a barrier. When area cost is not considered, SFMD is outperformed by an SPMD architecture on tasks with sparse communication and highly varying computation times. When communication is not too sparse, the ability of SFMD to allow more processors on a chip may compensate. Variance reduction techniques may also decrease the performance gap.

Identifier

doi:10.6083/M4NZ85MJ

Share

COinS
 
 

To view the content in your browser, please download Adobe Reader or, alternately,
you may Download the file to your hard drive.

NOTE: The latest versions of Adobe Reader do not support viewing PDF files within Firefox on Mac OS and if you are using a modern (Intel) Mac, there is no official plugin for viewing PDF files within the browser window.