Author

Bill Hostmann

Date

October 1987

Document Type

Thesis

Degree Name

M.S.

Department

Dept. of Computer Science and Engineering

Institution

Oregon Graduate Center

Abstract

Functional programming languages have been advanced as a means of increasing programmer productivity, enhancing program clarity and simplifying the task of program verification. The slow execution of functional programs on conventional computer architectures has been their major drawback. Several architectures have been proposed for executing functional programming languages more efficiently. One such architecture, the G-machine, provides architectural support for the evaluation of functional programming languages by graph reduction. In this study, designs for the instruction processing pipeline of the G-machine are examined and compared via simulation. A microcoded pipeline design, named Design 1, is proposed and its performance is evaluated using a range of enhancements which are known to reduce delays associated with instruction memory access and branches. While the enhancements increase performance, they also increase the complexity to implement the pipeline. A RISC design, Design 2, is then proposed for the instruction pipeline. Design 1 and Design 2 are compared, via simulation, to determine whether Design 2 can provide the functionality and throughput of Design 1. Recommendations for the design of the instruction pipeline of the G-machine are then made based on these simulations.

Identifier

doi:10.6083/M4Z0364X

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