August 1986

Document Type


Degree Name



Dept. of Computer Science and Engineering


Oregon Graduate Center


A dual-ported real memory architecture is described which supports the requirements of a list-processing evaluator, the G-machine. The architecture provides support for allocating available nodes and a concurrent garbage collection scheme. This scheme uses reference counts and requires traversal of sub-graphs to collect cyclic structures. The architecture requires only one customized hardware component that provides support for maintaining reference counts. Simulation of the architecture shows that it is efficient and meets the requirements of the G-machine given certain assumptions about the number and size of sub-graphs that are traversed. Cyclic structure information provided by the compiler would reduce the number of sub-graphs requiring traversal. Simulation shows that this optimization improves performance of the design, particularly for allocation rates greater than 100K nodes per second.





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